1. Technical Field
The present invention relates to a method for designing a semiconductor device, and to a method for evaluating reliability thereof.
2. Related Art
In recent years, for the purpose of satisfying the increasing requirements for achieving higher level of integration in a semiconductor device, copper becomes to be widely utilized for a material of interconnect lines or plugs. Copper is a material, which is characterized in having a lower resistance and a better electromigration resistance than that of aluminum that has been conventionally employed.
On the contrary, the generation of electromigration has become a problem in such type of the interconnect made of copper. FIG. 17 is a schematic cross sectional view of a copper multiple-layered interconnect formed via a damascene process. The copper multiple-layered interconnect has a configuration, in which an upper layer interconnect 30 is coupled to an upper portion of a lower layer interconnect 12 through a via 24. In such copper multiple-layered interconnect, a void 10 may be generated at an interface between the lower layer interconnect 12 and the via 24 due to a stress migration in copper, leading to a coupling failure between the interconnects. This causes problems of a reduction in a production yield of semiconductor devices or an unstable operation of semiconductor device in the long term use.
Japanese Patent Laid-Open No. H7-235,596 describes an interconnect structure of a semiconductor device, which include a lower layer interconnect formed on a base member and composed of an electrically conducting layer (barrier metal layer) and an aluminum-containing alloy layer formed thereon, an interlayer insulating layer formed on the base member and the lower layer interconnect, an opening formed in the interlayer insulating film above the lower layer interconnect and extending through the aluminum-containing alloy layer to the electrically conducting layer, and an upper layer interconnect formed in the opening and on the interlayer insulating layer and electrically coupled to the lower layer interconnect. It is described in Japanese Patent Laid-Open No. H7-235,596 that, since the opening extends through the aluminum-containing alloy layer to the electrically conducting layer, and the upper layer interconnect electrically coupled to the lower layer interconnect is formed in this opening, the upper layer interconnect is ensured to be electrically coupled to the lower layer interconnect even though voids are generated due to an electromigration and/or a stress migration in the aluminum-containing alloy layer located in vicinity of the bottom of the opening, thereby allowing to obtain the interconnect structure having higher reliability.
However, when a configuration including the via extending through the lower layer interconnect to contact with the barrier metal film on the bottom of the lower layer interconnect is employed as described in Japanese Patent Laid-Open No. H7-235,596, a barrier metal film of the via comes in contact with a barrier metal film of the lower layer interconnect, leading to a problem of an increased interconnect resistance. In particular, when the void is generated between the side wall of the via and the lower layer interconnect, the configuration including the electrical coupling between the barrier metal films exhibits unwanted higher resistance. Once such situation is attained, it is impossible to maintain lower resistance even if copper is employed for the interconnect material.